The L2 cache supports optional ECC in most of its memories. For core instruction and data accesses
resulting in an L2 cache hit, where a single-bit error is detected on the Data array, the L2
memory system supports in-line ECC correction. Uncorrected data is forwarded to the
requesting unit, and in parallel, the ECC circuitry checks for accuracy. If a single-bit error is
detected, any uncorrected data returned within two cycles before the error indicator must be
discarded. The L2 memory system begins to stream corrected data to the requestor.
When there is no data transfers, the L2 memory system shifts back to return uncorrected data
until it detects the next single-bit error. Forwarding uncorrected data can be disabled by
programming bit of the L2 Control Register. This avoids the requirement to flush requests associated with single-bit ECC errors on L2 cache
hits, but adds an additional 2 cycles to the L2 hit latency.
For all other single-bit ECC errors detected, the request is flushed from the L2 pipeline and is
forced to reissue. The tag bank where the single-bit error occurred, performs a
read-modify-write sequence to correct the single-bit error in the array. The request is then