7.7 External coherent interfaces

The Cortex-A72 processor provides configurable options for either AMBA4 AXI Coherency Extensions (ACE) or CHI interconnect architectures.

Each interface option provides a 128-bit wide data interface to the system and supports 1:1 clock ratios with respect to the processor clock and N:1, integer multiple clock ratios, of the core clock.

Note

ACE is supported with the following restriction:
  • ARQOS and AWQOS signals are not present.
This section contains the following subsections:
Non-ConfidentialPDF file icon PDF versionARM 100095_0002_04_en
Copyright © 2014-2016 ARM. All rights reserved.