7.7.4 Distributed virtual memory transactions

In a system where the processor can receive a Distributed Virtual Memory (DVM) synchronization message over the AXI master snoop address channel, BRESP for any write transaction must not be asserted to the core until all AXI masters that might have initiated the DVM synchronization request observe the transaction.


The Cortex-A72 processor does not support a multi-part DVM hint message.
Non-ConfidentialPDF file icon PDF versionARM 100095_0002_04_en
Copyright © 2014-2016 ARM. All rights reserved.