3.2.1 Execution state

The Execution state defines the processor execution environment, including:
  • Supported register widths.
  • Supported instruction sets.
  • Significant aspects of:
    • The execution model.
    • The Virtual Memory System Architecture (VMSA).
    • The programmers model.
The Execution states are:
AArch64
The 64-bit Execution state. This Execution state:
  • Features 31 64-bit general-purpose registers, with a 64-bit Program Counter (PC), Stack Pointer (SP), and Exception Link Registers (ELRs).
  • Provides a single instruction set, A64.
  • Defines the ARMv8 exception model, with four Exception levels, EL0-EL3, that provide an execution privilege hierarchy.
  • Features 48-bit Virtual Address (VA), held in 64-bit registers. The Cortex-A72 processor VMSA maps these to 44-bit Physical Address (PA) maps.
  • Defines a number of elements that hold the processor state (PSTATE). The A64 instruction set includes instructions that operate directly on various PSTATE elements.
  • Names each System register using a suffix that indicates the lowest Exception level that the register can be accessed.
AArch32
The 32-bit Execution state. This Execution state is backwards-compatible with implementations of the ARMv7-A architecture profile that include the Security Extensions and the Virtualization Extensions. This Execution state:
  • Features 13 32-bit general purpose registers, and a 32-bit PC, SP, and Link Register (LR). Some of these registers have multiple Banked instances for use in different processor modes.
  • Provides 32 64-bit registers for Advanced SIMD and Floating-point support.
  • Provides two instruction sets, A32 and T32.
  • Provides an exception model that maps the ARMv7 exception model onto the ARMv8 exception model and Exception levels. For exceptions taken to an Exception level that is using AArch32, this supports the ARMv7 exception model use of processor modes.
  • Features 32-bit VAs. The VMSA maps these to 40-bit PAs.
  • Collects processor state into the Current Processor State Register (CPSR).
The processor can move between Execution states only on a change of Exception level, and subject to the rules given in 3.2.4 Rules for changing Exception state. This means different software layers, such as an application, an operating system kernel, and a hypervisor, executing at different Exception levels, can execute in different Execution states.
Related information
3.2.7 Instruction set state
Non-ConfidentialPDF file icon PDF versionARM 100095_0002_04_en
Copyright © 2014-2016 ARM. All rights reserved.