4.1.1 Registers affected by CP15SDISABLE

The CP15SDISABLE signal disables write access to certain secure copies of System registers when EL3 is using AArch32. For a list of registers affected by CP15SDISABLE, see the ARM® Architecture Reference Manual ARMv8.
The Cortex-A72 processor does not have any IMPLEMENTATION DEFINED registers that are affected by CP15SDISABLE.
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