4.2.3 AArch64 virtual memory control registers

The following table shows the virtual memory control registers in AArch64 state. Bits[63:32] are reset to 0x00000000 for all 64-bit registers in the following table.

Table 4-3 AArch64 virtual memory control registers

Name Type Reset Width Description
SCTLR_EL1 RW 0x00C50838 32 4.3.30 System Control Register, EL1
SCTLR_EL2 RW 0x30C50838 32 System Control Register, EL2 
SCTLR_EL3 RW 0x00C50838a 32 4.3.38 System Control Register, EL3
TTBR0_EL1 RW UNK 64 Translation Table Base Address Register 0, EL1 b
TTBR1_EL1 RW UNK 64 Translation Table Base Address Register 1, EL1 b
TCR_EL1 RW UNK 64 4.3.41 Translation Control Register, EL1
TTBR0_EL2 RW UNK 64 Translation Table Base Address Register 0, EL2 b
TCR_EL2 RW UNK 32 4.3.42 Translation Control Register, EL2
VTTBR_EL2 RW UNK 64 Virtualization Translation Table Base Address Register, EL2 b
VTCR_EL2 RW UNK 32 4.3.43 Virtualization Translation Control Register, EL2
TTBR0_EL3 RW UNK 64 Translation Table Base Address Register 0, EL3 b
TCR_EL3 RW UNK 32 4.3.47 Translation Control Register, EL3
MAIR_EL1 RW UNK 64 Memory Attribute Indirection Register, EL1 b
AMAIR_EL1 RW RES0 64 4.3.56 Auxiliary Memory Attribute Indirection Register, EL1 and EL3
MAIR_EL2 RW UNK 64 Memory Attribute Indirection Register, EL2 b
AMAIR_EL2 RW RES0 64 4.3.57 Auxiliary Memory Attribute Indirection Register, EL2
MAIR_EL3 RW UNK 64 Memory Attribute Indirection Register, EL3 b
AMAIR_EL3 RW RES0 64 4.3.56 Auxiliary Memory Attribute Indirection Register, EL1 and EL3
CONTEXTIDR_EL1 RW UNK 32 Context ID Register, EL1 b
a The reset value depends on primary input CFGTE. Table 4-3 AArch64 virtual memory control registers assumes this signal is LOW.
b See the ARM® Architecture Reference Manual ARMv8 for more information.
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