4.2.8 AArch64 miscellaneous operations

The following table shows the miscellaneous operations in AArch64 state. See the ARM® Architecture Reference Manual ARMv8 for more information about these operations.

Table 4-9 AArch64 miscellaneous System operations

Name Type Reset Width Description
TPIDR_EL0 RW UNK 64
Thread Pointer / ID Register, EL0
TPIDR_EL1 RW UNK 64
Thread Pointer / ID Register, EL1
TPIDRRO_EL0 RW a UNK 64
Thread Pointer / ID Register, Read-Only, EL0
TPIDR_EL2 RW UNK 64
Thread Pointer / ID Register, EL2
TPIDR_EL3 RW UNK 64
Thread Pointer / ID Register, EL3
a
RO at EL0.
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