4.3.2 Multiprocessor Affinity Register, EL1

The MPIDR_EL1 characteristics are:

Purpose
Provides an additional core identification mechanism for scheduling purposes in a cluster system. EDDEVAFF0 is a read-only copy of MPIDR_EL1[31:0] accessible from the external debug interface.
Usage constraints
The accessibility to the MPIDR_EL1 by Exception level is:
EL0 EL1 (NS) EL1 (S) EL2 EL3 (SCR.NS = 1) EL3 (SCR.NS = 0)
- RO RO RO RO RO
The external debug accessibility to the EDDEVAFF0 by condition code is:
Off DLK OSLK EDAD SLK Default
- - - - - RO
Table 10-1 External register access conditions describes the condition codes.
Configurations
The MPIDR_EL1[31:0] is:
Attributes
See the register summary in Table 4-1 AArch64 identification registers.
The following figure shows the MPIDR_EL1 bit assignments.
Figure 4-2 MPIDR_EL1 bit assignments
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The following table shows the MPIDR_EL1 bit assignments.

Table 4-17 MPIDR_EL1 bit assignments

Bits Name Function
[63:32] - Reserved, RES0.
[31] - RES1.
[30] U
Indicates a single core system, as distinct from processor 0 in a cluster. This value is:
0Core is part of a cluster.
[29:25] - Reserved, RES0.
[24] MT
Indicates whether the lowest level of affinity consists of logical cores that are implemented using a multi-threading type approach. This value is:
0Performance of cores at the lowest affinity level is largely independent.
[23:16] Cluster ID Aff2
Affinity level 2. Second highest level affinity field.
Indicates the value read in at reset, from the CLUSTERIDAFF2 configuration signal.
[15:8] Cluster ID Aff1
Affinity level 1. Third highest level affinity field.
Indicates the value read in at reset, from the CLUSTERIDAFF1 configuration signal.
[7:2] - Reserved, RES0.
[1:0] CPU ID
Indicates the core number in the Cortex-A72 processor. The possible values are:
0x0A cluster with one processor only.
0x0, 0x1A cluster with two processors.
0x0, 0x1, 0x2 A cluster with three processors.
0x0, 0x1, 0x2, 0x3A cluster with four processors.
To access the MPIDR_EL1 in AArch64 state, read the register with:
MRS <Xt>, MPIDR_EL1; Read Multiprocessor Affinity Register
The EDDEVAFF0 can be accessed through the memory-mapped interface and the external debug interface, offset 0xFA8.
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