4.3.13 AArch32 Instruction Set Attribute Register 1, EL1

The ID_ISAR1_EL1 characteristics are:
Purpose
Provides information about the instruction set that the processor supports in AArch32.
Usage constraints
The ID_ISAR1_EL1 must be interpreted with:
  • ID_ISAR0_EL1.
  • ID_ISAR2_EL1.
  • ID_ISAR3_EL1.
  • ID_ISAR4_EL1.
  • ID_ISAR5_EL1.
The accessibility to the ID_ISAR1_EL1 by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- RO RO RO RO RO
Configurations
The ID_ISAR1_EL1 is:
  • Common to Secure and Non-secure states.
  • Architecturally mapped to the AArch32 ID_ISAR1 register.
Attributes
See the register summary in Table 4-1 AArch64 identification registers.
The following figure shows the ID_ISAR1_EL1 bit assignments.
Figure 4-12 ID_ISAR1_EL1 bit assignments
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The following table shows the ID_ISAR1_EL1 bit assignments.

Table 4-27 ID_ISAR1_EL1 bit assignments

Bits Name Function
[31:28] Jazelle Returns 0x1 to indicate the processor implements the BXJ instruction, and the J bit in the PSR.
[27:24] Interwork
Returns 0x3 to indicate the processor implements the following interworking instructions:
  • BX instruction, and the T bit in the PSR.
  • BLX instruction, and PC loads have BX-like behavior.
  • Data-processing instructions in the A32 instruction set with the PC as the destination and the S bit clear have BX-like behavior.
[23:20] Immediate
Returns 0x1 to indicate the processor implements the following data-processing instructions with long immediates:
  • MOVT instruction.
  • MOV instruction encoding with zero-extended 16-bit immediates.
  • Thumb ADD and SUB instruction encoding with zero-extended 12-bit immediates, and other ADD, ADR, and SUB encoding cross-referenced by the pseudocode for those encodings.
[19:16] IfThen Returns 0x1 to indicate the processor implements the IT instruction and the IT bits in the PSRs, in the T32 instruction set.
[15:12] Extend
Returns 0x2 to indicate the processor implements the following Extend instructions:
  • SXTB, SXTH, UXTB, and UXTH instructions.
  • SXTB16, SXTAB, SXTAB16, SXTAH, UXTB16, UXTAB, UXTAB16, and UXTAH instructions. See the ARM® Architecture Reference Manual ARMv8 for more information.
[11:8] Except_AR Returns 0x1 to indicate the processor implements the SRS, RFE, and CPS exception-handling instructions.
[7:4] Except Returns 0x1 to indicate the processor implements the LDM (exception return), LDM (user registers), and STM (user registers) exception-handling instructions in the A32 instruction set.
[3:0] Endian Returns 0x1 to indicate the processor implements the SETEND instruction, and the E bit in the PSRs.
To access the ID_ISAR1_EL1 in AArch64 state, read the register with:
MRS <Xt>, ID_ISAR1_EL1; Read AArch32 Instruction Set Attribute Register 1
To access the ID_ISAR1 in AArch32 state, read the CP15 register with:
MRC p15, 0, <Rt>, c0, c2, 1; Read AArch32 Instruction Set Attribute Register 1
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