4.3.26 Cache Type Register, EL0

The CTR_EL0 characteristics are:
Purpose
Provides information about the architecture of the caches.
Usage constraints
The accessibility to the CTR_EL0 in AArch64 state by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
Config RO RO RO RO RO
The accessibility to the CTR in AArch32 state by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- RO RO RO RO RO
Configurations
The CTR_EL0 is:
  • Common to Secure and Non-secure states.
  • Architecturally mapped to the AArch32 CTR register.
Attributes
See the register summary in Table 4-1 AArch64 identification registers.
The following figure shows the CTR_EL0 bit assignments.
Figure 4-24 CTR_EL0 bit assignments
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The following table shows the CTR_EL0 bit assignments.

Table 4-40 CTR_EL0 bit assignments

Bits Name Function
[31] - Reserved, RES1.
[30:28] - Reserved, RES0.
[27:24] CWG
Cache Writeback Granule. Log2 of the number of words of the maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified. This value is:
0x4Cache writeback granule size is 16 words.
[23:20] ERG
Exclusives Reservation Granule. Log2 of the number of words of the maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions. This value is:
0x4Exclusive reservation granule size is 16 words.
[19:16] DminLine
Log2 of the number of words in the smallest cache line of all the data and unified caches that the processor controls. This value is:
0x4Smallest data cache line size is 16 words.
[15:14] L1lp
Level 1 Instruction Cache policy. Indicates the indexing and tagging policy for the L1 Instruction Cache. This value is:
0b11Physical index, physical tag (PIPT).
[13:4] - Reserved, RES0.
[3:0] IminLine
Log2 of the number of words in the smallest cache line of all the Instruction Caches that the processor controls. This values is:
0x4Smallest Instruction Cache line size is 16 words.
To access the CTR_EL0 in AArch64 state, read the register with:
MRS <Xt>, CTR_EL0; Read Cache Type Register
To access the CTR in AArch32 state, read the CP15 register with:
MRC p15, 0, <Rt>, c0, c0, 1; Read Cache Type Register
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