4.3.27 Data Cache Zero ID, EL0

The DCZID_EL0 characteristics are:
Indicates the block size written with byte values of 0 by the DC ZVA, Data Cache Zero by Address, system instruction.
Usage constraints
The accessibility of the DCZID_EL0 by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
The DCZID_EL0 is a 32-bit register.
See the register summary in Table 4-1 AArch64 identification registers.
The following figure shows the DCZID_EL0 bit assignments.
Figure 4-25 DCZID_EL0 bit assignments
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The following table shows the DCZID_EL0 bit assignments.

Table 4-41 DCZID_EL0 bit assignments

Bits Name Function
[63:5] - Reserved, RES0.
[4] DZP
Prohibit the DC ZVA instruction. The possible values are:
0DC ZVA instruction permitted. This is the reset value.
1DC ZVA instruction prohibited.
[3:0] BS Returns 0x4 to indicate that the block size is 16 words.
To access the DCZID_EL0 in AArch64 state, read or write the register with:
MRS <Xt>, DCZID_EL0; Read Data Cache Zero ID Register
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