4.3.32 Architectural Feature Access Control Register, EL1

The CPACR_EL1 characteristics are:
Purpose
Controls access to trace functionality and access to registers associated with Floating-point and Advanced SIMD execution.
Usage constraints
The accessibility of the CPACR_EL1 by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- RW RW RW RW RW
Configurations
The CPACR_EL1 is:
  • A32-bit register in AArch64 state.
  • Architecturally mapped to the Non-secure AArch32 CPACR register.
Attributes
See the register summary in Table 4-4 AArch64 other System registers.
The following figure shows the CPACR_EL1 bit assignments.
Figure 4-29 CPACR_EL1 bit assignments
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The following table shows the CPACR_EL1 bit assignments.

Table 4-45 CPACR_EL1 bit assignments

Bits Name Function
[31:29] - Reserved, RES0.
[28] TTA
Traps trace functionality to EL1 when executing from EL0 or EL1. The value is:
0System register access to trace functionality is not supported. This bit is RES0.
[27:22] - Reserved, RES0.
[21:20] FPEN
Traps instructions that access registers associated with floating-point and SIMD execution to trap to EL1 when executed from EL0 or EL1. The possible values are:
0b000b10Trap any instruction in EL0 or EL1 that use registers associated with floating-point and Advanced SIMD execution. The reset value is 0b00.
0b01Trap any instruction in EL0 that use registers associated with floating-point and Advanced SIMD execution. Instructions in EL1 are not trapped.
0b11No instructions are trapped.
[19:0] - Reserved, RES0.
To access the CPACR_EL1 in AArch64 state, read or write the register with:
MRS <Xt>, CPACR_EL1; Read EL1 Architectural Feature Access Control Register
MSR CPACR_EL1, <Xt>; Write EL1 Architectural Feature Access Control Register
Related information
4.5.6 Architectural Feature Access Control Register
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