4.3.43 Virtualization Translation Control Register, EL2

The VTCR_EL2 characteristics are:
Purpose
Controls the translation table walks required for the stage 2 translation of memory accesses from Non-secure EL0 and EL1, and holds cacheability and shareability information for the accesses.
Usage constraints
The accessibility to the VTCR_EL2 by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- - - RW RW RW
Configurations
The VTCR_EL2 is:
  • A32-bit register in AArch64 state.
  • Architecturally mapped to the AArch32 VTCR register.
Attributes
See the register summary in Table 4-3 AArch64 virtual memory control registers.
The following figure shows the VTCR_EL2 bit assignments.
Figure 4-39 VTCR_EL2 bit assignments
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The following table shows the VTCR_EL2 bit assignments.

Table 4-55 VTCR_EL2 bit assignments

Bits Name Function
[31] - Reserved, RES1.
[30:19] - Reserved, RES0.
[18:16] PS
Physical Address Size. The possible values are:
0b00032-bit, 4GBytes.
0b00136-bit, 64GBytes.
0b01040-bit, 1TByte.
0b01142-bit, 4TBytes.
0b10044-bit, 16TBytes.
0b10148-bit, 256TBytes.
All other values are reserved.
[15] - Reserved, RES0.
[14] TG0
Granule size for the corresponding TTBR0_ELx.
04KB.
164KB.
[13:12] SH0
Shareability attribute for memory associated with translation table walks using TTBR0:
0b00Non-shareable.
0b01Reserved.
0b11Outer Shareable.
0b11Inner Shareable.
[11:10] ORGN0
Outer cacheability attribute for memory associated with translation table walks using TTBR0.
0b00Normal memory, Outer Non-cacheable.
0b01Normal memory, Outer Write-Back Write-Allocate Cacheable.
0b11Normal memory, Outer Write-Through Cacheable.
0b11Normal memory, Outer Write-Back no Write-Allocate Cacheable.
[9:8] IRGN0
Inner cacheability attribute for memory associated with translation table walks using TTBR0.
0b00Normal memory, Inner Non-cacheable.
0b01Normal memory, Inner Write-Back Write-Allocate Cacheable.
0b11Normal memory, Inner Write-Through Cacheable.
0b11Normal memory, Inner Write-Back no Write-Allocate Cacheable.
[7:6] SL0 Starting level of the VTCR_EL2 addressed region.
[5:0] T0SZ The size offset of the memory region addressed by TTBR0. The region size is 2(64–T0SZ) bytes.
To access the VTCR_EL2 in AArch64 state, read or write the register with:
MRS <Xt>, VTCR_EL2; Read EL2 Virtualization Translation Control Register
MSR VTCR_EL2, <Xt>; Write EL2 Virtualization Translation Control Register
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