4.3.55 Physical Address Register, EL1

The PAR_EL1 characteristics are:
Purpose
The Physical Address returned from an address translation.
Usage constraints
The accessibility of the PAR_EL1 by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- RW RW RW RW RW
Configurations
The architectural mapping of the PAR_EL1 is to the Non-secure AArch32 PAR register.
Attributes
See the register summary in Table 4-8 AArch64 address translation operations.
The following figure shows the PAR_EL1 bit assignments when the Virtual Address to Physical Address conversion completes successfully.
Figure 4-48 PAR_EL1 pass bit assignments
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The following table shows the PAR_EL1 bit assignments when the Virtual Address to Physical Address conversion completes successfully.

Table 4-67 PAR_EL1 pass bit assignments

Bits Name Function
[63:60] AttrH
Defines Device memory or Normal memory plus Outer cacheability. Must be used in conjunction with AttrL. The possible values are:
0x0Device memory, see AttrL.
0x4Normal memory, Outer Non-cacheable.
0x8Normal memory, Outer Write-Through Cacheable.
0x9Normal memory, Outer Write-Through Cacheable, Outer Write-Allocate.
0xANormal memory, Outer Write-Through Cacheable, Outer Read-Allocate.
0xBNormal memory, Outer Write-Through Cacheable, Outer Write-Allocate, Outer Read-Allocate.
0xCNormal memory, Outer Write-Back Cacheable.
0xDNormal memory, Outer Write-Back Cacheable, Outer Write-Allocate.
0xENormal memory, Outer Write-Back Cacheable, Outer Read-Allocate.
0xFNormal memory, Outer Write-Back Cacheable, Outer Write-Allocate, Outer Read-Allocate.
All other values are reserved.
[59:56] AttrL
Defines Device memory or Normal memory plus Inner cacheability. Must be interpreted in conjunction with AttrH. The possible values are:
0x0Device-nGnRnE memory if AttrH is 0x0. Otherwise this value is reserved.
0x4Device memory if AttrH is 0x0. Otherwise, Normal memory, Inner Non-cacheable.
0x8Reserved if AttrH is 0x0. Otherwise, Normal memory, Inner Write-Through Cacheable.
0x9Reserved if AttrH is 0x0. Otherwise, Normal memory, Inner Write-Through Cacheable, Inner Write-Allocate.
0xAReserved if AttrH is 0x0. Otherwise, Normal memory, Inner Write-Through Cacheable, Inner Read-Allocate.
0xBReserved if AttrH is 0x0. Otherwise, Normal memory, Inner Write-Through Cacheable, Inner Write-Allocate, Inner Read-Allocate.
0xCReserved if AttrH is 0x0. Otherwise, Normal memory, Inner Write-Back Cacheable.
0xDReserved if AttrH is 0x0. Otherwise, Normal memory, Inner Write-Back Cacheable, Inner Write-Allocate.
0xEReserved if AttrH is 0x0. Otherwise, Normal memory, Inner Write-Back Cacheable, Inner Read-Allocate.
0xFReserved if AttrH is 0x0. Otherwise, Normal memory, Inner Write-Through Cacheable, Inner Write-Allocate, Inner Read-Allocate.
All other values are reserved.
[55:44] - Reserved, RES0.
[43:12] PA Physical address. The Physical Address corresponding to the supplied Virtual Address. Returns address bits[31:12].
[11] - Reserved, RES1.
[10] - Reserved, RES0.
[9] NS
Non-secure. The NS attribute for a translation table entry read from Secure state.
This bit is UNKNOWN for a translation table entry from Non-secure state.
[8:7] SHA
Shareability attribute for the Physical Address returned from a translation table entry. The values are:
0b00Non-shareable.
0b01Reserved.
0b10Outer Shareable.
0b11Inner Shareable.

Note

The SHA bit takes the value of 0b10 for:
  • Any type of device memory.
  • Normal memory with both Inner Non-cacheable and Outer-cacheable attributes.
[6:1] - Reserved, RES0.
[0] F
Pass/Fail bit. Indicates whether the conversion completed successfully. This value is:
0Virtual Address to Physical Address conversion completed successfully.
The following figure shows the PAR_EL1 bit assignments when the Virtual Address to Physical Address conversion aborts.
Figure 4-49 PAR_EL1 fail bit assignments
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The following table shows the PAR_EL1 bit assignments when the Virtual Address to Physical Address conversion aborts.

Table 4-68 PAR_EL1 fail bit assignments

Bits Name Function
[63:12] - Reserved, RES0.
[11] - Reserved, RES1.
[10] - Reserved, RES0.
[9] S
Stage of fault. Indicates the state where the translation aborted. The values are:
0Translation aborted because of a fault in stage 1 translation.
1Translation aborted because of a fault in stage 2 translation.
[8] PTW
Indicates a stage 2 fault during a stage 1 table walk. The values are:
0No stage 2 fault during a stage 1 table walk.
1Translation aborted because of a stage 2 fault during a stage 1 table walk.
[7] - Reserved, RES0.
[6:1] FST
Fault status code, as shown in the Data Abort ESR encoding. See the ARM® Architecture Reference Manual ARMv8 for more information.
[0] F
Pass/Fail bit. Indicates whether the conversion completed successfully. The value is:
1Virtual Address to Physical Address conversion aborted.
To access the PAR_EL1 in AArch64 state, read or write the register with:
MRS <Xt>, PAR_EL1; Read EL1 Physical Address Register
MSR PAR_EL1, <Xt>; Write EL1 Physical Address Register
Related information
4.5.18 Physical Address Register
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