4.3.58 L2 Control Register, EL1

The L2CTLR_EL1 characteristics are:

Purpose
Provides IMPLEMENTATION DEFINED control options for the L2 memory system and ECC/parity support. There is one L2 Control Register for the Cortex-A72 processor.
Usage constraints
The accessibility to the L2CTLR_EL1 by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- RWa RWa RWb RW RW

Note

The L2CTLR_EL1 must be set statically and not dynamically changed.
The L2 Control Register can only be written when the L2 memory system is idle. ARM recommends that you write to this register after a powerup reset before the MMU is enabled and before any ACE, CHI, or ACP traffic begins.
If the register must be modified after a powerup reset sequence, you must idle the L2 memory system with the following sequence:
  1. Disable the MMU from each processor followed by an ISB to ensure the MMU disable operation is complete, then execute a DSB to drain previous memory transactions.
  2. Ensure that the system has no outstanding AC channel or CHI RXRSP coherence requests to the processor.
  3. Ensure that the system has no outstanding ACP requests to the processor.
When the L2 is idle, the processor can update the L2 Control Register followed by an ISB. After the L2 Control Register is updated, you can enable the MMUs and normal ACE or CHI and ACP traffic can resume.
Configurations
The L2CTLR_EL1 is:
  • Common to the Secure and Non-secure states.
  • A 32-bit register in AArch64 state.
  • Architecturally mapped to the AArch32 L2CTLR register.
Attributes
See the register summary in Table 4-15 AArch64 IMPLEMENTATION DEFINED registers.
The following figure shows the L2CTLR_EL1 bit assignments.
Figure 4-50 L2CTRL_EL1 bit assignments
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The following table shows the L2CTLR_EL1 bit assignments.

Table 4-69 L2CTLR_EL1 bit assignments

Bits Name Function
[31] L2RSTDISABLE monitor
Monitors the L2 hardware reset disable signal, L2RSTDISABLE. The values are:
0L2 valid RAM contents are reset by hardware.
1L2 valid RAM contents are not reset by hardware.
This bit is read-only. The primary input L2RSTDISABLE controls the reset value.
[30:26] - Reserved, RES0.
[25:24] Number of processors
Number of processors present. These bits are read-only and set to the number of processors present in the implementation. The values are:
0b00One processor, CPU0.
0b01Two processors, CPU0 and CPU1.
0b10Three processors, CPU0, CPU1, and CPU2.
0b11Four processors, CPU0, CPU1, CPU2, and CPU3.
[23] L2 Cache protection
This bit is read-only and is set if the cluster implementation supports L2 cache ECC protection. The L2 cache ECC protection is a configurable implementation option in Cortex-A72 cluster. The values are:
0
L2 cache ECC is not supported.
1
L2 cache ECC is supported.
[22] L1 Cache ECC and Parity protection
This bit is read-only and is set if the processor implementation supports L1 cache ECC and parity protection. The L1 cache ECC and parity protection is a configurable implementation option in Cortex-A72 processor. The values are:
0L1 data cache ECC and L1 instruction cache parity is not supported.
1L1 data cache ECC and L1 instruction cache parity is supported.
[21] ECC and parity enable
ECC and parity enable. The values are:
0
Disables ECC and parity. This is the reset value.
1
Enables ECC and parity.
If Cortex-A72 is implemented with L1 Cache ECC and parity protection, L2CTLR[21] can be programmed to enable or disable both L1 ECC and parity and L2 ECC protection.
If Cortex-A72 is implemented with no L1 Cache ECC and parity protection but with L2 ECC protection, L2CTLR[21] can be programmed to enable or disable only L2 ECC protection.
If Cortex-A72 is implemented with neither L1 ECC and parity nor L2 ECC protection, L2CTLR[21] is RAZ/WI.
[20] Data inline ECC enable, only applies if ECC is enabled
Force inline ECC for Instruction Fetch (IF) and Load/Store (LS) read requests that hit the L2 cache increasing the L2 hit latency by 2 cycles. Avoids requirement of flushing requests associated with L2 cache single-bit ECC errors. The possible values are:
0Performance optimization reducing L2 hit latency by 2 cycles allowing uncorrected data for IF and LS read requests that hit the L2 cache. This is the reset value.
1Forward only corrected data for L2 cache hits avoiding flushing request for single-bit ECC errors.
[19:14] - Reserved, RES0.
[13] L2 arbitration slice
L2 arbitration slice. This is a read-only bit that is set if the L2 arbitration slice is present in the implementation. The values are:
0L2 arbitration slice is not present.
1One L2 arbitration slice is present.
[12] L2 Tag RAM slice
L2 Tag RAM slice. This is a read-only bit that is set if the Tag RAM slice is present in the implementation. The values are:
0L2 Tag RAM slice is not present.
1One L2 Tag RAM slice is present.
[11:10] L2 Data RAM slice
L2 Data RAM slice. These are read-only bits that are set to the number of Data RAM slices present in the implementation. The values are:
0b00L2 Data RAM slices are not present.
0b01One L2 Data RAM slice is present.
0b10Two L2 Data RAM slices are present.
0b11Invalid value.
[9] L2 Tag RAM setup
L2 Tag RAM setup. The values are:
00 cycle. This the reset value.
11 cycle.
[8:6] L2 Tag RAM latency
L2 Tag RAM latency. The L2 Tag RAM programmable setup and latency bits only affect the L2 Tag RAM. See 7.2.5 Register slice support for large cache sizes for more information. The possible values are:
0b0002 cycles. This is the reset value.
0b0012 cycles.
0b0103 cycles.
0b0114 cycles.
0b1xx5 cycles.
[5] L2 Data RAM setup
L2 Data RAM setup. The values are:
00 cycle. This the reset value.
11 cycle.
[4:3] -
Reserved, RES0.
[2:0] L2 Data RAM latency
L2 Data RAM latency.c The L2 Data RAM programmable setup & latency bits affect only the L2 Data RAM. See 7.2.5 Register slice support for large cache sizes for more information. The values are:
0b000
2 cycles. This is the reset value.
0b001
2 cycles.
0b010
3 cycles.
0b011
4 cycles.
0b100
5 cycles.
0b101
6 cycles.
0b11x
6 cycles.
To access the L2CTLR_EL1 in AArch64 state, read or write the register with:
MRS <Xt>, S3_1_c11_c0_2; Read L2 Control Register
MSR S3_1_c11_c0_2, <Xt>; Write L2 Control Register
To access the L2CTLR in AArch32 state, read or write the CP15 register with:
MRC p15, 1, <Rt>, c9, c0, 2; Read L2 Control Register
MCR p15, 1, <Rt>, c9, c0, 2; Write L2 Control Register
a Write access if ACTLR_EL3.L2CTLR is 1 and ACTLR_EL2.L2CTLR is 1, or, ACTLR_EL3.L2CTLR is 1 and the Secure SCR.NS is 0.
b Write access if ACTLR_EL3.L2CTLR is 1.
c Slice and Set-up have priority over programmed latency in determining total adjusted pipeline depth.
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