4.3.62 Instruction L1 Data n Register, EL1

The IL1DATAn_EL1, where n is from 0 to 3, characteristics are:
Purpose
Holds the instruction side L1 array information returned by the RAMINDEX system operation.

Note

Because all of the I-side arrays are greater than 32-bit wide, the processor contains multiple IL1DATA registers, to hold the array information.
Usage constraints
The accessibility to the IL1DATAn_EL1 by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- RW RW RW RW RW
Configurations
The IL1DATAn_EL1 is:
  • Common to the Secure and Non-secure states.
  • A 32-bit register in AArch64 state.
  • Architecturally mapped to the AArch32 IL1DATAn registers.
Attributes
See the register summary in Table 4-15 AArch64 IMPLEMENTATION DEFINED registers.
The following figure shows the IL1DATAn_EL1 bit assignments.
Figure 4-54 IL1DATA
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The following table shows the IL1DATAn_EL1 bit assignments.

Table 4-73 IL1DATAn_EL1 bit assignments

Bits Name Function
[31:0] Data Holds the instruction side L1 array information
To access the IL1DATAn_EL1 in AArch64 state, read or write the registers with:
MRS <Xt>, s3_0_c15_c0_n; Read EL1 Instruction L1 Data n Register
MSR s3_0_c15_c0_n, <Xt>; Write EL1 Instruction L1 Data n Register
n is 0, 1, 2, or 3 for Opcode2 of IL1DATAn_EL1 registers.
To access the IL1DATAn in AArch32 state, read or write the CP15 registers with:
MRC p15, 0, <Rt>, c15, c0, n; Read Instruction L1 Data n Register
MCR p15, 0, <Rt>, c15, c0, n; Write Instruction L1 Data n Register
n is 0, 1, 2, or 3 for Opcode2 of IL1DATAn registers.
Related information
4.3.64 RAM Index operation
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