The CBAR_EL1 characteristics are:
- Holds the physical base address of the memory-mapped
GIC CPU interface registers.
- Usage constraints
The accessibility to the CBAR_EL1 by Exception level
||EL3(SCR.NS = 1)
||EL3(SCR.NS = 0)
The CBAR_EL1 is:
- Common to the Secure and Non-secure states.
- A 64-bit register in AArch64 state.
- See the register summary in Table 4-15 AArch64 IMPLEMENTATION DEFINED registers.
The following figure shows the
CBAR_EL1 bit assignments.
Figure 4-78 CBAR_EL1 bit assignments
The following table shows the CBAR_EL1
Table 4-82 CBAR_EL1 bit assignments
||The primary input PERIPHBASE[43:18] determines
the reset value
To access the CBAR_EL1 in AArch64 state, read the register
MRS <Xt>, s3_1_c15_c3_0; Read EL1 Configuration Base Address Register