4.4.3 c2 registers

The following table shows the System registers when CRn is c2 and the processor is in AArch32 state.

Table 4-86 c2 register summary

op1 CRm op2 Name Type Reset Description
0 c0 0 TTBR0 RW UNK 4.5.14 Translation Table Base Register 0 and Register 1
    1 TTBR1 RW UNK
    2 TTBCR RW 0x00000000a 4.5.15 Translation Table Base Control Register
4 c0 2 HTCR RW UNK 4.5.16 Hyp Translation Control Register
  c1 2 VTCR RW UNK Virtualization Translation Control Register, see the ARM® Architecture Reference Manual ARMv8
a The reset value is 0x00000000 for the Secure copy of the register. The reset value for the EAE bit of the Non-secure copy of the register is 0b0. You must program the Non-secure copy of the register with the required initial value, as part of the processor boot sequence.
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