4.4.5 c5 registers

The following table shows the System registers when CRn is c5 and the processor is in AArch32 state.

Table 4-88 c5 register summary

op1 CRm op2 Name Type Reset Description
0 c0 0 DFSR RW UNK 4.5.17 Data Fault Status Register.
  1 IFSR RW UNK Instruction Fault Status Register. See 4.3.51 Instruction Fault Status Register, EL2.
  c1 0 ADFSR RW 0x00000000 Auxiliary Data Fault Status Register. See 4.3.48 Auxiliary Fault Status Register 0, EL1 and EL3.
  1 AIFSR RW 0x00000000 Auxiliary Instruction Fault Status Register. See 4.3.49 Auxiliary Fault Status Register 1, EL1 and EL3.
4 c1 0 HADFSR RW 0x00000000 Hyp Auxiliary Data Fault Status Register. See 4.3.52 Auxiliary Fault Status Register 0, EL2 and Hyp Auxiliary Data Fault Status Register.
  1 HAIFSR RW 0x00000000 Hyp Auxiliary Instruction Fault Status Register. See 4.3.53 Auxiliary Fault Status Register 1, EL2 and Hyp Auxiliary Instruction Fault Status Register.
  c2 0 HSR RW UNK Hyp Syndrome Register. See 4.3.54 Exception Syndrome Register, EL2.
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