4.4.6 c6 registers

The following table shows the System registers when CRn is c6 and the processor is in AArch32 state. See the ARM® Architecture Reference Manual ARMv8 for more information about these registers.

Table 4-89 c6 register summary

op1 CRm op2 Name Type Reset Description
0 c0 0 DFAR RW UNK Data Fault Address Register
    2 IFAR RW UNK Instruction Fault Address Register
4 c0 0 HDFAR RW UNK Hyp Data Fault Address Register
  2 HIFAR RW UNK Hyp Instruction Fault Address Register
  4 HPFAR RW UNK Hyp IPA Fault Address Register
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