4.4.8 c7 System operations

The following table shows the System operations when CRn is c7 and the processor is in AArch32 state. See the ARM® Architecture Reference Manual ARMv8 for more information about these operations.

Table 4-91 c7 System operation summary

op1 CRm op2 Name Description
0 c1 0 ICIALLUIS Invalidate all instruction caches Inner Shareable to PoUa
  6 BPIALLIS Invalidate all entries from branch predictors Inner Shareable
  c5 0 ICIALLU Invalidate all Instruction Caches to PoU
  1 ICIMVAU Invalidate Instruction Caches by VA to PoU
  4 CP15ISB Instruction Synchronization Barrier operation, this operation is deprecated in ARMv8-A
  6 BPIALL Invalidate all entries from branch predictors
  7 BPIMVA Invalidate VA from branch predictors
  c6 1 DCIMVAC Invalidate data cache line by VA to PoCb
  2 DCISW Invalidate data cache line by set/way
  c8 0 ATS1CPR Stage 1 current state PL1 read
  1 ATS1CPW Stage 1 current state PL1 write
  2 ATS1CUR Stage 1 current state unprivileged read
  3 ATS1CUW Stage 1 current state unprivileged write
  4 ATS12NSOPR Stages 1 and 2 Non-secure only PL1 read
  5 ATS12NSOPW Stages 1 and 2 Non-secure only PL1 write
  6 ATS12NSOUR Stages 1 and 2 Non-secure only unprivileged read
  7 ATS12NSOUW Stages 1 and 2 Non-secure only unprivileged write
  c10 1 DCCMVAC Clean data cache line by VA to PoC
  2 DCCSW Clean data cache line by set/way
  4 CP15DSB Data Synchronization Barrier operation, this operation is deprecated in ARMv8-A
  5 CP15DMB Data Memory Barrier operation, this operation is deprecated in ARMv8-A
  c11 1 DCCMVAU Clean data cache line by VA to PoU
  c14 1 DCCIMVAC Clean and invalidate data cache line by VA to PoC
  2 DCCISW Clean and invalidate data cache line by set/way
4 c8 0 ATS1HR Stage 1 Hyp mode read
  1 ATS1HW Stage 1 Hyp mode write
a PoU = Point of Unification. PoU is set by the BROADCASTINNER signal and can be in the L1 data cache or outside of the processor, in which case PoU is dependent on the external memory system.
b PoC = Point of Coherence. The PoC is always outside of the processor and is dependent on the external memory system.
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