4.4.14 c14 registers

The following table shows the System registers when CRn is C14 and the processor is in AArch32 state. See the ARM® Architecture Reference Manual ARMv8 for more information about these registers.

Table 4-97 c14 register summary

op1 CRm op2 Name Type Reset Description
0 c0 0 CNTFRQ RW a UNK Timer Counter Frequency register
  c1 0 CNTKCTL RW -b EL1 Timer Control register
  c2 0 CNTP_TVAL RW UNK EL1 Physical Timer TimerValue register
  1 CNTP_CTL RW - EL1 Physical Timer Control register
  c3 0 CNTV_TVAL RW UNK Virtual Timer TimerValue register
  1 CNTV_CTL RW -c Virtual Timer Control register
  c8 0 PMEVCNTR0 RW UNK Performance Monitors Event Count Registers
    1 PMEVCNTR1
    2 PMEVCNTR2
    3 PMEVCNTR3
    4 PMEVCNTR4
    5 PMEVCNTR5
  c12 0 PMEVTYPER0 RW UNK Performance Monitors Event Type Registers
    1 PMEVTYPER1
    2 PMEVTYPER2
    3 PMEVTYPER3
    4 PMEVTYPER4
    5 PMEVTYPER5
  c15 7 PMCCFILTR RW 0x00000000 Performance Monitors Cycle Count Filter Register
4 c1 0 CNTHCTL RW -d EL2 Timer Control register
  c2 0 CNTHP_TVAL RW UNK EL2 Physical Timer TimerValue register
  1 CNTHP_CTL RW -c EL2 Physical Timer Control register
a Ar EL3(S) only, otherwise it is RO.
b The reset value for bits[9:8, 2:0] is 0b00000.
c The reset value for bit[0] is 0.
d The reset value for bit[2] is 0 and for bits[1:0] is 0b11.
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