4.4.16 64-bit registers

The following table gives a summary of the 64-bit wide System registers, accessed by the MCRR and MRRC instructions when the processor is in AArch32 state.

Table 4-99 64-bit register summary

CRn op1 CRm op2 Name Type Reset Description
- 0 c2 - TTBR0 RW UNK Translation Table Base Register 0. 
- 1 c2 - TTBR1 RW UNK Translation Table Base Register 1. a
- 4 c2 - HTTBR RW UNK Hyp Translation Table Base Register. a
- 6 c2 - VTTBR RW UNKb Virtualization Translation Table Base Register. a
- 0 c7 - PAR RW UNK 4.5.18 Physical Address Register.
- 0 c9 - PMCCNTR RW - Performance Monitors Cycle Count Register. a
- 0 c14 - CNTPCT RO UNK Physical Timer Count register. a
- 1 c14 - CNTVCT RO UNK Virtual Timer Count register. a
- 2 c14 - CNTP_CVAL RW UNK EL1 Physical Timer CompareValue register. a
- 3 c14 - CNTV_CVAL RW UNK Virtual Timer CompareValue register. a
- 4 c14 - CNTVOFF RW UNK Virtual Timer Offset register. a
- 6 c14 - CNTHP_CVAL RW UNK EL2 Physical Timer CompareValue register. a
  0 c15 - CPUACTLR RW -c CPU Auxiliary Control Register. See 4.3.66 CPU Auxiliary Control Register, EL1.
  1 c15 - CPUECTLR RW -d CPU Extended Control Register. See 4.3.67 CPU Extended Control Register, EL1.
- 2 c15 - CPUMERRSR RW - CPU Memory Error Syndrome Register. See 4.3.68 CPU Memory Error Syndrome Register, EL1.
- 3 c15 - L2MERRSR RW -e L2 Memory Error Syndrome Register. See 4.3.69 L2 Memory Error Syndrome Register, EL1.
a See the ARM® Architecture Reference Manual ARMv8 for more information.
b The reset value for bits[55:48] is zero.
c 
The reset value is zero.
d The reset value is 0x0000 001B 0000 0000.
e 
The reset value for bits[63,47:40,39:32,31] is zero.
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