4.4.17 Identification registers

The following table shows the Identification registers in AArch32 state.

Table 4-100 Identification registers

Name CRn op1 CRm op2 Type Reset Description
MIDR c0 0 c0 0 RO 0x410FD082 Main ID Register. See 4.3.1 Main ID Register, EL1.
CTR       1 RO 0x8444C004 Cache Type Register. See 4.3.26 Cache Type Register, EL0.
TCMTR       2 - 0x00000000 4.5.1 TCM Type Register.
TLBTR       3 RO 0x00000000 4.5.2 TLB Type Register.
MPIDR       5 RO 0x80000003a 4.5.3 Multiprocessor Affinity Register.
REVIDR       6 RO 0x00000000 Revision ID Register. See 4.3.3 Revision ID Register, EL1.
MIDR       4, 7 RO 0x410FD082 Aliases of Main ID Register, see 4.3.1 Main ID Register, EL1.
ID_PFR0     c1 0 RO 0x00000131 Processor Feature Register 0. See 4.3.4 AArch32 Processor Feature Register 0, EL1.
ID_PFR1       1 RO 0x00011011b Processor Feature Register 1. See 4.3.5 AArch32 Processor Feature Register 1, EL1.
ID_DFR0       2 RO 0x03010066 Debug Feature Register 0. See 4.3.6 AArch32 Debug Feature Register 0, EL1.
ID_AFR0       3 RO 0x00000000 Auxiliary Feature Register 0. See 4.3.7 AArch32 Auxiliary Feature Register 0, EL1.
ID_MMFR0       4 RO 0x10201105 Memory Model Feature Register 0. See 4.3.8 AArch32 Memory Model Feature Register 0, EL1.
ID_MMFR1       5 RO 0x40000000 Memory Model Feature Register 1. See 4.3.9 AArch32 Memory Model Feature Register 1, EL1.
ID_MMFR2       6 RO 0x01260000 Memory Model Feature Register 2. See 4.3.10 AArch32 Memory Model Feature Register 2, EL1.
ID_MMFR3       7 RO 0x02102211 Memory Model Feature Register 3. See 4.3.11 AArch32 Memory Model Feature Register 3, EL1.
ID_ISAR0     c2 0 RO 0x02101110 Instruction Set Attribute Register 0. See 4.3.12 AArch32 Instruction Set Attribute Register 0, EL1
ID_ISAR1       1 RO 0x13112111 Instruction Set Attribute Register 1. See 4.3.13 AArch32 Instruction Set Attribute Register 1, EL1.
ID_ISAR2       2 RO 0x21232042 Instruction Set Attribute Register 2. See 4.3.14 AArch32 Instruction Set Attribute Register 2, EL1.
ID_ISAR3       3 RO 0x01112131 Instruction Set Attribute Register 3. See 4.3.15 AArch32 Instruction Set Attribute Register 3, EL1.
ID_ISAR4       4 RO 0x00011142 Instruction Set Attribute Register 4. See 4.3.16 AArch32 Instruction Set Attribute Register 4, EL1.
ID_ISAR5       5 RO 0x00010001c Instruction Set Attribute Register 5. See 4.3.17 AArch32 Instruction Set Attribute Register 5, EL1.
CCSIDR   1 c0 0 RO UNK Cache Size ID Register. See 4.3.22 Cache Size ID Register, EL1.
CLIDR       1 RO 0x0A200023 Cache Level ID Register. See 4.3.23 Cache Level ID Register, EL1.
AIDR       7 - 0x00000000 Auxiliary ID Register. See 4.3.24 Auxiliary ID Register, EL1.
CSSELR   2 c0 0 RW UNK Cache Size Selection Register. See 4.3.25 Cache Size Selection Register, EL1.
VPIDR   4 c0 0 RW -d Virtualization Processor ID Register. See 4.3.28 Virtualization Processor ID Register, EL2.
VMPIDR       5 RO -e Virtualization Multiprocessor ID Register. See 4.5.4 Virtualization Multiprocessor ID Register.
a The reset value depends on the primary inputs, CLUSTERIDAFF1, and the number of processors that the MPCore device implements. The value shown is for a four processor implementation, with CLUSTERIDAFF1 set to zero.
b The reset value depends on the primary input GICCDISABLE. The value shown assumes the GICCDISABLE signal is tied HIGH.
c The reset value is 0x00011121 if the Cryptography engine is implemented.
d The reset value is the value of the Main ID Register. See 4.3.1 Main ID Register, EL1 for more information.
e The reset value is the value of the Multiprocessor Affinity Register.
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