4.4.18 CPUID registers

The following table shows the CPUID registers in AArch32 state.

Table 4-101 CPUID registers

Name CRn op1 CRm op2 Type Reset Description
ID_PFR0 c0 0 c1 0 RO 0x00000131 Processor Feature Register 0. See 4.3.4 AArch32 Processor Feature Register 0, EL1.
ID_PFR1 1 RO 0x00011011a Processor Feature Register 1. See 4.3.5 AArch32 Processor Feature Register 1, EL1.
ID_DFR0 2 RO 0x03010066 Debug Feature Register 0. See 4.3.6 AArch32 Debug Feature Register 0, EL1.
ID_AFR0 3 RO 0x00000000 Auxiliary Feature Register 0. See 4.3.7 AArch32 Auxiliary Feature Register 0, EL1.
ID_MMFR0 4 RO 0x10201105 Memory Model Feature Register 0. See 4.3.8 AArch32 Memory Model Feature Register 0, EL1.
ID_MMFR1 5 RO 0x40000000 Memory Model Feature Register 1. See 4.3.9 AArch32 Memory Model Feature Register 1, EL1.
ID_MMFR2 6 RO 0x01260000 Memory Model Feature Register 2. See 4.3.10 AArch32 Memory Model Feature Register 2, EL1.
ID_MMFR3 7 RO 0x02102211 Memory Model Feature Register 3. See 4.3.11 AArch32 Memory Model Feature Register 3, EL1.
ID_ISAR0 c0 0 c2 0 RO 0x02101110 Instruction Set Attribute Register 0. See 4.3.12 AArch32 Instruction Set Attribute Register 0, EL1.
ID_ISAR1 1 RO 0x13112111 Instruction Set Attribute Register 1. See 4.3.13 AArch32 Instruction Set Attribute Register 1, EL1.
ID_ISAR2 2 RO 0x21232042 Instruction Set Attribute Register 2. See 4.3.14 AArch32 Instruction Set Attribute Register 2, EL1.
ID_ISAR3 3 RO 0x01112131 Instruction Set Attribute Register 3. See 4.3.15 AArch32 Instruction Set Attribute Register 3, EL1.
ID_ISAR4 4 RO 0x00011142 Instruction Set Attribute Register 4. See 4.3.16 AArch32 Instruction Set Attribute Register 4, EL1.
ID_ISAR5 5 RO 0x00000001b Instruction Set Attribute Register 5. See 4.3.17 AArch32 Instruction Set Attribute Register 5, EL1.
a The reset value depends on the primary input GICCDISABLE. The value shown assumes the GICCDISABLE signal is tied HIGH.
b The reset value is 0x00001121 if the Cryptography engine is implemented.
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