4.4.19 Virtual memory control registers

The following table shows the Virtual memory control registers in AArch32 state.

Table 4-102 Virtual memory control registers

Name CRn op1 CRm op2 Type Reset Width Description
SCTLR c1 0 c0 0 RW 0x00C50838a 32-bit 4.5.5 System Control Register.
HSCTLR c1 4 c0 0 RW 0x30C50838 32-bit Hyp System Control Register. 
TTBR0 c2 0 c0 0 RW UNK 32-bit Translation Table Base Register 0. b
- 0 c2 - 64-bit
TTBR1 c2 0 c0 1 RW UNK 32-bit Translation Table Base Register 1. b
- 1 c2 - 64-bit
TTBCR c2 0 c0 2 RW 0x00000000c 32-bit 4.5.15 Translation Table Base Control Register.
HTCR c2 4 c0 2 RW UNK 32-bit 4.5.16 Hyp Translation Control Register.
VTCR   c1 2 RW UNK 32-bit Virtualization Translation Control Register. b
DACR c3 0 c0 0 RW UNK 32-bit Domain Access Control Register. b
PRRR c10 0 c2 0 RW 0x00098AA4 32-bit 4.5.19 Primary Region Remap Register.
MAIR0     0 RW UNK 32-bit 4.5.20  Memory Attribute Indirection Register 0.
NMRR     1 RW 0x44E048E0 32-bit 4.5.21 Normal Memory Remap Register..
MAIR1     1 RW UNK 32-bit 4.5.22  Memory Attribute Indirection Register 1.
AMAIR0     c3 0 RW UNK 32-bit Auxiliary Memory Attribute Indirection Register 0. See 4.3.56 Auxiliary Memory Attribute Indirection Register, EL1 and EL3.
AMAIR1     1 RW UNK 32-bit Auxiliary Memory Attribute Indirection Register 1. See 4.3.56 Auxiliary Memory Attribute Indirection Register, EL1 and EL3.
HMAIR0   4 c2 0 RW UNK 32-bit Hyp Memory Attribute Indirection Register 0. b
HMAIR1     1 RW UNK 32-bit Hyp Memory Attribute Indirection Register 1. b
HAMAIR0     c3 0 RW UNK 32-bit Hyp Auxiliary Memory Attribute Indirection Register 0. See 4.3.57 Auxiliary Memory Attribute Indirection Register, EL2.
HAMAIR1     1 RW UNK 32-bit Hyp Auxiliary Memory Attribute Indirection Register 1. See 4.3.57 Auxiliary Memory Attribute Indirection Register, EL2.
CONTEXTIDR c13 0 c0 1 RW UNK 32-bit Context ID Register. b
a The reset value depends on primary inputs, CFGTE, CFGEND, and VINITHI. Table 4-102 Virtual memory control registers assumes these signals are LOW.
b See the ARM® Architecture Reference Manual ARMv8 for more information.
c The reset value is 0x00000000 for the Secure copy of the register. The reset value for the EAE bit of the Non-secure copy of the register is 0x0. You must program the Non-secure copy of the register with the required initial value, as part of the processor boot sequence.
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