4.4.22 Cache maintenance operations

The following table shows the System instructions for cache and branch predictor maintenance operations in AArch32 state. See the ARM® Architecture Reference Manual ARMv8 for more information about these operations.

Table 4-105 Cache and branch predictor maintenance operations

Name CRn op1 CRm op2 Description
ICIALLUIS c7 0 c1 0
Instruction Cache invalidate all to PoUa Inner Shareable
BPIALLIS     6 Branch predictor invalidate all Inner Shareable
ICIALLU     c5 0 Instruction Cache invalidate all to PoU
ICIMVAU     1 Instruction Cache invalidate by VA to PoU
BPIALL     6 Branch predictor invalidate all
BPIMVA     7 Branch predictor invalidate by VA
DCIMVAC     c6 1 Data cache invalidate by VA to PoCb
DCISW     2 Data cache invalidate by set/way
DCCMVAC     c10 1 Data cache clean by VA to PoC
DCCSW     2 Data cache clean by set/way
DCCMVAU     c11 1 Data cache clean by VA to PoU
DCCIMVAC     c14 1 Data cache clean and invalidate by VA to PoC
DCCISW     2 Data cache clean and invalidate by set/way
a PoU = Point of Unification. PoU is set by the BROADCASTINNER signal and can be in the L1 data cache or outside of the processor, in which case PoU is dependent on the external memory system.
b PoC = Point of Coherence. The PoC is always outside of the processor and is dependent on the external memory system.
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