4.4.23 TLB maintenance operations

The following table shows the System instructions for TLB maintenance operations in AArch32 state. See the ARM® Architecture Reference Manual ARMv8 for more information about these operations.

Table 4-106 TLB maintenance operations

Name CRn op1 CRm op2 Description
TLBIALLIS c8 0 c3 0 Invalidate entire unified TLB Inner Shareable
TLBIMVAIS     1 Invalidate unified TLB by VA and ASID Inner Shareable
TLBIASIDIS     2 Invalidate unified TLB by ASID Inner Shareable
TLBIMVAAIS     3 Invalidate unified TLB by VA all ASID Inner Shareable
TLBIMVALIS     5 Invalidate unified TLB entry by VA Inner Shareable, Last level
TLBIMVAALIS     7 Invalidate unified TLB by VA all ASID Inner Shareable, Last level
ITLBIALL     c5 0 Invalidate entire instruction TLB
ITLBIMVA     1 Invalidate instruction TLB entry by VA and ASID
ITLBIASID     2 Invalidate instruction TLB by ASID
DTLBIALL     c6 0 Invalidate entire data TLB
DTLBIMVA     1 Invalidate data TLB entry by VA and ASID
DTLBIASID     2 Invalidate data TLB by ASID
TLBIALL     c7 0 Invalidate entire unified TLB
TLBIMVA     1 Invalidate unified TLB by VA and ASID
TLBIASID     2 Invalidate unified TLB by ASID
TLBIMVAA     3 Invalidate unified TLB by VA all ASID
TLBIMVAL     5 Invalidate unified TLB entry by VA, Last level
TLBIMVAAL     7 Invalidate unified TLB by VA all ASID, Last level
The Virtualization registers include additional TLB operations for use in Hyp mode.
Related information
4.2.13 AArch64 EL2 TLB maintenance operations
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