4.4.26 Performance Monitors registers

The following table shows the Performance Monitors registers in AArch32 state.

Table 4-110 Performance Monitors registers

Name CRn op1 CRm op2 Type Reset Description
PMCR c9 0 c12 0 RW 0x41023000 Performance Monitors Control Register. See 11.4.1 Performance Monitors Control Register, EL0.
PMCNTENSET     1 RW UNK Performance Monitors Count Enable Set Register. 
PMCNTENCLR     2 RW UNK Performance Monitors Count Enable Clear Register. a
PMOVSR     3 RW UNK Performance Monitors Overflow Flag Status Register. a
PMSWINC     4 WO - Performance Monitors Software Increment Register. a
PMSELR     5 RW UNK Performance Monitors Event Counter Selection Register. a
PMCEID0     6 RO 0x7FFF0F3F Performance Monitors Common Event Identification Register 0. See 11.4.2 Performance Monitors Common Event Identification Register 0, EL0.
PMCEID1     7 RO UNK Performance Monitors Common Event Identification Register 1. a
PMCCNTR     c13 0 RW UNK Performance Monitors Cycle Count Register. a
PMXEVTYPER     1 RW UNK Performance Monitors Selected Event Type Register. a
PMCCFILTR       RW 0x00000000 Performance Monitors Cycle Count Filter Register. a
PMXEVCNTR     2 RW UNK Performance Monitors Selected Event Count Register. a
PMUSERENR     c14 0 RW 0x00000000 Performance Monitors User Enable Register. a
PMINTENSET     1 RW UNK Performance Monitors Interrupt Enable Set Register. a
PMINTENCLR     2 RW UNK Performance Monitors Interrupt Enable Clear Register. a
PMOVSSET     3 RW UNK Performance Monitors Overflow Flag Status Set Register. a
a See the ARM® Architecture Reference Manual ARMv8 for more information.
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