4.4.28 Virtualization registers

The following table shows the Virtualization registers in AArch32 state.

Table 4-112 Virtualization registers

Name CRn op1 CRm op2 Type Reset Width Description
VPIDR c0 4 c0 0 RW -a 32-bit Virtualization Processor ID Register. See 4.3.28 Virtualization Processor ID Register, EL2.
VMPIDR       5 RO -b 32-bit 4.5.4 Virtualization Multiprocessor ID Register.
HSCTLR c1 4 c0 0 RW 0x30C50838 32-bit Hyp System Control Register.
HACTLR     1 RW 0x00000000 32-bit Hyp Auxiliary Control Register. See 4.3.33 Auxiliary Control Register, EL2.
HCR   c1 0 RW 0x00000000 32-bit 4.5.10 Hyp Configuration Register.
HDCR     1 RW 0x00000006d 32-bit 4.5.12 Hyp Debug Control Register.
HCPTR     2 RW 0x000033FF 32-bit 4.5.13 Hyp Architectural Feature Trap Register.
HSTR     3 RW 0x00000000 32-bit Hyp System Trap Register. See 4.3.36 Hypervisor System Trap Register.
HCR2     4 RW 0x00000000 32-bit 4.5.11 Hyp Configuration Register 2.
HACR     7 RW 0x00000000 32-bit 4.3.37 Hyp Auxiliary Configuration Register.
HTCR c2 4 c0 2 RW UNK 32-bit 4.5.16 Hyp Translation Control Register.
VTCR     c1 2 RW UNK 32-bit Virtualization Translation Control Register. c
HTTBR - 4 c2 - RW UNK 64-bit Hyp Translation Table Base Register. c
VTTBR - 6 c2 - RW UNKe 64-bit Virtualization Translation Table Base Register. c
HADFSR c5 4 c1 0 RW UNK 32-bit Hyp Auxiliary Data Fault Status Register. See 4.3.52 Auxiliary Fault Status Register 0, EL2 and Hyp Auxiliary Data Fault Status Register.
HAIFSR     1 RW UNK 32-bit Hyp Auxiliary Instruction Fault Status Register. See 4.3.53 Auxiliary Fault Status Register 1, EL2 and Hyp Auxiliary Instruction Fault Status Register.
HSR     c2 0 RW UNK 32-bit Hyp Syndrome Register. See 4.3.54 Exception Syndrome Register, EL2.
HDFAR c6 4 c0 0 RW -f 32-bit Hyp Data Fault Address Register. c
HIFAR     2 RW -g 32-bit Hyp Instruction Fault Address Register. c
HPFAR     4 RW UNK 32-bit Hyp IPA Fault Address Register. c
HMAIR0 c10 4 c2 0 RW UNK 32-bit Hyp Memory Attribute Indirection Register 0. c
HMAIR1     1 RW UNK 32-bit Hyp Memory Attribute Indirection Register 1. c
HAMAIR0     c3 0 RW UNK 32-bit Hyp Auxiliary Memory Attribute Indirection Register 0. See 4.3.57 Auxiliary Memory Attribute Indirection Register, EL2.
HAMAIR1     1 RW UNK 32-bit Hyp Auxiliary Memory Attribute Indirection Register 1. See 4.3.57 Auxiliary Memory Attribute Indirection Register, EL2.
HVBAR c12 4 c0 0 RW UNK 32-bit Hyp Vector Base Address Register. c
a The reset value is the value of the Main ID Register.
b The reset value is the value of the Multiprocessor Affinity Register.
c See the ARM® Architecture Reference Manual ARMv8 for more information.
d The reset value for bit[7] is UNK.
e The reset value for bits[55:48] is 0b00000000.
f The reset value is the value of the Secure copy of the DFAR register.
g The reset value is the value of the Secure copy of the IFR register.
Non-ConfidentialPDF file icon PDF versionARM 100095_0002_04_en
Copyright © 2014-2016 ARM. All rights reserved.