4.5.2 TLB Type Register

The TLBTR characteristics are:
Provides information about the TLB implementation.
Usage constraints
The accessibility to the TLBTR by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
The TLBTR is Common to Secure and Non-secure states.
See the register summary in Table 4-84 c0 register summary.
The following figure shows the TLBTR bit assignments.
Figure 4-79 TLBTR bit assignments
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The following table shows the TLBTR bit assignments.

Table 4-115 TLBTR bit assignments

Bits Name Function
[31:1] - Reserved, RES0.
[0] nU
Not Unified. Indicates whether the implementation has a unified TLB. The value is:
0Processor has a unified TLB.
To access the TLBTR in AArch32 state, read the CP15 register with:
MRC p15, 0, <Rt>, c0, c0, 3; Read TLB Type Register
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