4.5.7 Secure Configuration Register

The SCR characteristics are:
Purpose
Defines the configuration of the current Security state. It specifies:
  • The Security state of the processor, Secure or Non-secure.
  • What mode the processor branches to, if an IRQ, FIQ, or external abort occurs.
  • Whether the CPSR.F and CPSR.A bits can be modified when SCR.NS is 1.
If EL3 is using AArch64, accesses to this register from Secure EL1 using AArch32 are trapped to EL3.
Usage constraints
The accessibility to the SCR by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- - TRAP - RW RW
Configurations
The SCR is a Restricted access register that exists only in the Secure state.
The SCR is mapped to the AArch64 SCR_EL3 register.
AttributesSee the register summary in Table 4-85 c1 register summary.
The following figure shows the SCR bit assignments.
Figure 4-84 SCR bit assignments
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The following table shows the SCR bit assignments.

Table 4-120 SCR bit assignments

Bits Name Function
[31:14] - Reserved, RES0.
[13] TWE
Trap WFE instructions. The possible values are:
0WFE instructions are not trapped. This is the reset value.
1WFE instructions executed in any mode other than Monitor mode that would cause suspended execution as if the event register is not set, there is not a pending WFE wake-up event and the instruction does not cause another exception, is trapped to Monitor mode using the UNDEFINED exception vector.
[12] TWI
Trap WFI instructions. The possible values are:
0WFI instructions are not trapped. This is the reset value.
1WFI instructions executed in any mode other than Monitor mode that would cause suspended execution, as if there is no pending WFI wake-up event and the instruction does not cause another exception, is trapped to Monitor mode using the UNDEFINED exception vector.
[11:10] - Reserved, RES0.
[9] SIF
Secure Instruction Fetch. When the processor is in Secure state, this bit disables instruction fetches from Non-secure memory. The possible values are:
0Secure state instruction fetches from Non-secure memory permitted. This is the reset value.
1Secure state instruction fetches from Non-secure memory not permitted.
[8] HCE
Hyp Call enable. This bit enables the use of HVC instruction. The possible values are:
0The HVC instruction is UNDEFINED in any mode. This is the reset value.
1The HVC instruction enabled in Non-secure EL1 or EL2, and performs a Hyp Call.
[7] SCD
Secure Monitor Call disable. This bit causes the SMC instruction to be UNDEFINED in all privileged modes. The possible values are:
0The SMC instruction executes normally from privileged modes, and performs a Secure Monitor Call. This is the reset value.
1The SMC instruction is UNDEFINED in any mode.
A trap of the SMC instruction to Hyp mode from Non-secure EL1 takes priority over the value of this bit. See the ARM® Architecture Reference Manual ARMv8 for more information.
[6] nET
Not Early Termination. This bit disables early termination.
This bit is not implemented, RES0.
[5] AW
A bit writable. This bit controls whether CPSR.A can be modified in Non-secure state. For the Cortex-A72 processor:
  • This bit has no effect on whether CPSR.A can be modified in Non-secure state. The AW bit can be modified in either Security state.
  • This bit, with the HCR.AMO bit, determines whether CPSR.A has any effect on exceptions that are routed to a Non-secure mode.
[4] FW
F bit writable. This bit controls whether CPSR.F can be modified in Non-secure state. For the Cortex-A72 processor:
  • This bit has no effect on whether CPSR.F can be modified in Non-secure state. The FW bit can be modified in either Security state.
  • This bit, with the HCR.FMO bit, determines whether CPSR.F has any effect on exceptions that are routed to a Non-secure mode.
[3] EA
External Abort handler. This bit controls which mode takes external aborts. The possible values are:
0External aborts taken in Abort mode. This is the reset value.
1External aborts taken in Monitor mode.
[2] FIQ
FIQ handler. This bit controls which mode takes FIQ exceptions. The possible values are:
0FIQs taken in FIQ mode. This is the reset value.
1FIQs taken in Monitor mode.
[1] IRQ
IRQ handler. This bit controls which mode takes IRQ exceptions. The possible values are:
0IRQs taken in IRQ mode. This is the reset value.
1IRQs taken in Monitor mode.
[0] NS
Non-secure bit. Except when the processor is in Monitor mode, this bit determines the Security state of the processor. The possible values are:
0Secure. This is the reset value.
1Non-secure.

Note

When the processor is in Monitor mode, it is always in Secure state, regardless of the value of the NS bit.
To access the SCR in AArch32 state, read or write the CP15 register with:
MRC p15, 0, <Rt>, c1, c1, 0; Read Secure Configuration Register data
MCR p15, 0, <Rt>, c1, c1, 0; Write Secure Configuration Register data
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