ARM Cortex-A72 MPCore Processor Technical Reference Manual : 4.5.9 Secure Debug Configuration Register

4.5.9 Secure Debug Configuration Register

The SDCR characteristics are:

Purpose

Controls the trapping to Hyp mode of Secure accesses, at EL1 or lower, to functions provided by the debug and trace architectures.

If EL3 is using AArch64, accesses to this register from Secure EL1 using AArch32 are trapped to EL3.

Usage constraints

The accessibility to the SDCR by Exception level is:

EL0	EL1(NS)	EL1(S)	EL2	EL3(SCR.NS = 1)	EL3(SCR.NS = 0)
-	-	TRAP	-	RW	RW

Configurations

The SDCR is a Restricted access register that only exists in the Secure state.

The SDCR is mapped to the AArch64 MDCR_EL3 register.

Attributes

See the register summary in Table 4-85 c1 register summary.

The following figure shows the SDCR bit assignments.

Figure 4-86 SDCR bit assignments

The following table shows the SDCR bit assignments

Table 4-122 SDCR bit assignments

Bits Name Function

[31:22] - Reserved, RES0.

[21]

EPMAD

Disables access to the performance monitor configuration registers by an external debugger:

0	External debugger access to the performance monitor configuration registers enabled. This is the reset value.
1	External debugger access to the performance monitor configuration registers disabled, unless overridden by the authentication interface.

Resets to 0 on Warm reset.

[20]

EDAD

Disables access to the breakpoint and watchpoint registers by an external debugger:

0	External debugger access to the breakpoint and watchpoint registers enabled. This is the reset value.
1	External debugger access to the breakpoint and watchpoint registers disabled, unless overridden by the authentication interface.

Resets to 0 on Warm reset.

[19:18] - Reserved, RES0.

[17]

SPME

Enables Secure performance monitor:

0	Performance monitors disabled in Secure state, no events are counted. This is the reset value.
1	Performance monitors enabled in Secure state.

Resets to 0 on Warm reset.

[16] - Reserved, RES0.

[15:14]

SPD^a

AArch32 Secure privileged debug. Enables or disables debug exceptions from Secure state if Secure EL1 is using AArch32, other than Software breakpoint instructions. The possible values are:

`0b00`	Legacy mode. Debug exceptions from Secure EL1 are enabled if `AArch32SelfHostedSecurePrivilegedInvasiveDebugEnabled()` is true.
`0b10`	Secure privileged debug disabled. Debug exceptions from Secure EL1 are disabled.
`0b11`	Secure privileged debug enabled. Debug exceptions from Secure EL1 are enabled.

The value 0b01 is reserved.

Note

If debug exceptions from Secure EL1 are enabled, then debug exceptions from Secure EL0 are also enabled. Otherwise, debug exceptions from Secure EL0 are enabled only if SDER32_EL3.SUIDEN is 1.

Ignored if Secure EL1 is using AArch64 and in Non-secure state. Debug exceptions from Software breakpoint instruction debug events are always enabled.

Resets to 0 on Warm reset.

[13:0] - Reserved, RES0.

To access the SDCR in AArch32 state, read or write the CP15 register with:

MRC p15, 0, <Rt>, c1, c3, 1; Read Secure Debug Configuration Register
MCR p15, 0, <Rt>, c1, c3, 1; Write Secure Debug Configuration Register

^a SPD only applies in Secure state and when either Secure EL1 or EL3 is using AArch32.

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