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Home > System Control > AArch32 register descriptions > Secure Debug Configuration Register |
EL0 | EL1(NS) | EL1(S) | EL2 | EL3(SCR.NS = 1) | EL3(SCR.NS = 0) |
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- | - | TRAP | - | RW | RW |
Table 4-122 SDCR bit assignments
Bits | Name | Function | ||||||
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[31:22] | - | Reserved, RES0. | ||||||
[21] | EPMAD | Disables access to the
performance monitor configuration registers by an external debugger:
Resets to 0 on Warm reset.
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[20] | EDAD | Disables access to the
breakpoint and watchpoint registers by an external debugger:
Resets to 0 on Warm reset.
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[19:18] | - | Reserved, RES0. | ||||||
[17] | SPME | Enables Secure performance
monitor:
Resets to 0 on Warm reset.
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[16] | - | Reserved, RES0. | ||||||
[15:14] | SPDa | AArch32 Secure privileged debug.
Enables or disables debug exceptions from Secure state if Secure EL1 is using
AArch32, other than Software breakpoint instructions. The possible values are:
The value
0b01 is
reserved.NoteIf debug exceptions from Secure EL1 are enabled, then debug
exceptions from Secure EL0 are also enabled. Otherwise, debug exceptions from
Secure EL0 are enabled only if SDER32_EL3.SUIDEN is 1.
Ignored if Secure EL1 is using AArch64 and in Non-secure
state. Debug exceptions from Software breakpoint instruction debug events are
always enabled.
Resets to 0 on Warm reset.
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[13:0] | - | Reserved, RES0. |
MRC p15, 0, <Rt>, c1, c3, 1; Read Secure Debug Configuration Register MCR p15, 0, <Rt>, c1, c3, 1; Write Secure Debug Configuration Register