4.5.11 Hyp Configuration Register 2

The HCR2 characteristics are:
Purpose
Provides additional configuration controls for virtualization.
Usage constraints
The accessibility to the HCR2 in AArch32 state by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- - - RW RW -
Configurations
The HCR2 is:
  • A Banked EL2 register.
  • Architecturally mapped to the AArch64 HCR_EL2[63:31] register.
Attributes
See the register summary in Table 4-85 c1 register summary.
The following figure shows the HCR2 bit assignments.
Figure 4-88 HCR2 bit assignments
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The following table shows the HCR2 bit assignments.

Table 4-124 HCR2 bit assignments

Bits Name Function
[31:2] - Reserved, RES0.
[1] ID
Stage 2 Instruction Cache disable. When HCR_EL2.VM is 1, this forces all stage2 translations for instruction accesses to Normal memory to be Non-cacheable for the EL1/EL0 translation regime. The values are:
0No effect on the stage 2 of the EL1/EL0 translation regime for instruction accesses. This is the reset value.
1Forces all stage 2 translations for instruction accesses to Normal memory to be Non-cacheable for the EL0/EL1 translation regime.
[0] CD
Stage 2 Data cache disable. When HCR_EL2.VM is 1, this forces all stage2 translations for data accesses and translation table walks to Normal memory to be Non-cacheable for the EL1/EL0 translation regime. The values are:
0No effect on the stage 2 of the EL1/EL0 translation regime for data accesses and translation table walks. This is the reset value.
1Forces all stage 2 translations for data accesses and translation table walks to Normal memory to be Non-cacheable for the EL0/EL1 translation regime.
To access the HCR2 in AArch32 state, read or write the CP15 register with:
MRC p15, 4, <Rt>, c1, c1, 4; Read Hyp Configuration Register 2
MCR p15, 4, <Rt>, c1, c1, 4; Write Configuration Register 2
Related information
4.3.34 Hypervisor Configuration Register, EL2
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