4.5.12 Hyp Debug Control Register

The HDCR characteristics are:
Purpose
Controls the trapping to Hyp mode of Non-secure accesses, at EL1 or lower, to functions provided by the debug and trace architectures.
Usage constraints
The accessibility to the HDCR in AArch32 state by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- - - RW RW -
Configurations
The HDCR is:
  • A Banked EL2 register.
  • Architecturally mapped to the AArch64 MDCR_EL2 register.
Attributes
See the register summary in Table 4-85 c1 register summary.
The following figure shows the HDCR bit assignments.
Figure 4-89 HDCR bit assignments
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The following table shows the HDCR bit assignments.

Table 4-125 HDCR bit assignments

Bits Name Function
[31:12] - Reserved, RES0.
[11] TDRA
Trap Debug ROM Access. The values are:
0Has no effect on Debug ROM accesses. This is the reset value.
1Trap valid Non-secure EL0 or EL1 Debug ROM accesses to Hyp mode.
When this bit is set to 1, any valid Non-secure access to DBGDRAR or DBGDSAR is trapped to Hyp mode.
If bit[8], TDE, is set, or if the HCR.TGE bit is set, the TDRA value is ignored and the processor behaves as if this bit is set to 1.
[10] TDOSA
Trap Debug OS-related register Access. The values are:
0Has no effect on accesses to CP14 Debug registers. This is the reset value.
1Trap valid EL0 or EL1 Non-secure accesses to CP14 OS-related Debug registers to Hyp mode.
When this bit is set to 1, any valid Non-secure CP14 access to the following OS-related Debug registers is trapped to Hyp mode:
  • DBGOSLSR.
  • DBGOSLAR.
  • DBGOSDLR.
  • DBGPRCR.
If bit[8], TDE, is set, or if the HCR.TGE bit is set, the TDRA value is ignored and the processor behaves as if this bit is set to 1.
[9] TDA
Trap Debug Access. The values are:
0Has no effect on accesses to CP14 Debug registers. This is the reset value.
1Trap valid EL0 or EL1 Non-secure accesses to CP14 Debug registers to Hyp mode.
When this bit is set to 1, any valid Non-secure access to the CP14 Debug registers, other than the registers trapped by the TDRA and TDOSA bits, is trapped to Hyp mode.
If bit[8], TDE, is set, or if the HCR.TGE bit is set, the TDRA value is ignored and the processor behaves as if this bit is set to 1.
[8] TDE
Trap Debug Exceptions. The values are:
0Has no effect on Debug exceptions. This is the reset value.
1Trap valid Non-secure Debug exceptions to Hyp mode.
When this bit is set to 1, any Debug exception taken in Non-secure state is trapped to Hyp mode.
When this bit is set to 1, the TRA, TDOSA, and TDA bits are treated as if they are set to 1, irrespective of the value stored in the register. If the HCR.TGE bit is set to 1, this bit is treated as if it was set to 1, irrespective of the value stored in the register.
[7] HPME
Hypervisor Performance Monitors Enable. The values are:
0Hyp mode Performance Monitors counters disabled. This is the reset value.
1Hyp mode Performance Monitors counters enabled.
When this bit is set to 1, access to the Performance Monitors counters that are reserved for use from Hyp mode is enabled. For more information, see the description of the HPMN field.
[6] TPM
Trap Performance Monitors accesses. The values are:
0Has no effect on Performance Monitors accesses. This is the reset value.
1Trap valid Non-secure Performance Monitors accesses to Hyp mode.
When this bit is set to 1, any valid Non-secure EL0 or EL1 access to the Performance Monitors registers is trapped to Hyp mode.
[5] TPMCR
Trap Performance Monitors Control Register accesses. The values are:
0Has no effect on PMCR accesses. This is the reset value.
1Trap valid Non-secure PMCR accesses to Hyp mode.
When this bit is set to 1, any valid Non-secure access to the PMCR is trapped to Hyp mode.
[4:0] HPMN
Defines the number of Performance Monitors counters that are accessible from Non-secure EL1, and from Non-secure EL0 if unprivileged access is enabled.
This field behaves as if it contains an UNKNOWN value of less than or equal to PMCR.N, in all ways other than when reading back this field if:
  • This field is set to 0.
  • This field is set to a value greater than PMCR.N.
In Non-secure state, HPMN divides the Performance Monitors counters as follows:
If PMXEVCNTR is accessing Performance Monitors counter n then, in Non-secure state:
  • If n is in the range 0 ≤ n < HPMN, the counter is accessible from EL1 and EL2, and from EL0 if unprivileged access to the counters is enabled.
  • If n is in the range HPMN ≤ n < PMCR.N, the counter is accessible only from EL2. The HPME bit enables access to the counters in this range.
This field resets to 0x6, the value of PMCR.N.
To access the HDCR in AArch32 state, read or write the CP15 register with:
MRC p15, 4, <Rt>, c1, c1, 1; Read Hyp Debug Configuration Register
MCR p15, 4, <Rt>, c1, c1, 1; Write Hyp Debug Configuration Register
To access the MDCR_EL2 in AArch64 state, read or write the register with:
MRS <Xt>, MDCR_EL2; Read Monitor Debug Configuration Register
MSR MDCR_EL2, <Xt>; Write Monitor Debug Configuration Register
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