4.5.13 Hyp Architectural Feature Trap Register

The HCPTR characteristics are:
Purpose
Controls the trapping to Hyp mode of Non-secure accesses, at EL1 or lower, to coprocessors other than CP14 and CP15 and to floating-point and Advanced SIMD functionality. The HCPTR also controls the access to this functionality from Hyp mode.
Usage constraints
The accessibility to the HCPTR by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- - - RW RW -
If a bit in the NSACR prohibits a Non-secure access, then the corresponding bit in the HCPTR behaves as RES1 for Non-secure accesses. See the bit descriptions for more information.
Configurations
The HCPTR is:
  • A Banked EL2 register.
  • Architecturally mapped to the AArch64 CPTR_EL2 register.
Attributes
See the register summary in Table 4-85 c1 register summary.
The following figure shows the HCPTR bit assignments.
Figure 4-90 HCPTR bit assignments
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The following table shows the HCPTR bit assignments.

Table 4-126 HCPTR bit assignments

Bits Name Function
[31] TCPAC
Trap Coprocessor Access Control Register accesses. When this bit is set to 1, any valid Non-secure EL1 accesses to the CPACR is trapped to Hyp mode. The values are:
0Has no effect on CPACR accesses. This is the reset value.
1Trap valid Non-secure EL1 CPACR accesses to Hyp mode.
[30:21] - Reserved, UNK/RES0.
[20] TTA
Trap Trace Access. This value is:
0CP14 access to the trace registers is not supported.
[19:16] - Reserved, UNK/RES0.
[15] TASE
Trap Advanced SIMD use. If NSACR.NSASEDIS is set to 1, this bit behaves as RES1 on Non-secure accesses. The values are:
0
If the NSACR settings permit Non-secure use of the Advanced SIMD functionality then Hyp mode can access that functionality, regardless of any settings in the CPACR. This is the reset value.

Note

This bit value has no effect on possible use of the Advanced SIMD functionality from Non-secure EL1 and EL0.
1
Trap valid Non-secure accesses to Advanced SIMD functionality to Hyp mode.
When this bit is set to 1, any otherwise-valid access to Advanced SIMD functionality from:
  • A Non-secure EL1 or EL0 access is trapped to Hyp mode.
  • Hyp mode generates an UNDEFINED Instruction exception, taken in Hyp mode.

Note

If TCP10 and TCP11 are set to 1, then all Advanced SIMD use is trapped to Hyp mode, regardless of the value of this field.
[14] - Reserved, RES0.
[13:12] - Reserved, RES1.
[11] TCP11
Trap coprocessor 11. The values are:
0
If NSACR.CP11 is set to 1, then Hyp mode can access CP11, regardless of the value of CPACR.CP11. This is the reset value.

Note

This bit value has no effect on possible use of CP11 from Non-secure EL1 and EL0.
1
Trap valid Non-secure accesses to CP11 to Hyp mode.
When TCP11 is set to 1, any otherwise-valid access to CP11 from:
  • A Non-secure EL1 or EL0 access is trapped to Hyp mode.
  • Hyp mode generates an Undefined Instruction exception, taken in Hyp mode.
[10] TCP10
Trap coprocessor 10. The possible values are:
0
If NSACR.CP10 is set to 1, then Hyp mode can access CP10, regardless of the value of CPACR.CP10. This is the reset value.

Note

This bit value has no effect on possible use of CP10 from Non-secure EL1 and EL0.
1
Trap valid Non-secure accesses to CP10 to Hyp mode.
When TCP10 is set to 1, any otherwise-valid access to CP10 from:
  • A Non-secure EL1 or EL0 access is trapped to Hyp mode.
  • Hyp mode generates an Undefined Instruction exception, taken in Hyp mode.
[9:0] - Reserved, RES1.
To access the HCPTR in AArch32 state, read or write the CP15 register with:
MRC p15, 4, <Rt>, c1, c1, 2; Read Hyp Architectural Feature Trap Register
MCR p15, 4, <Rt>, c1, c1, 2; Write Hyp Architectural Feature Trap Register
Related information
4.5.8 Non-secure Access Control Register
4.3.35 Architectural Feature Trap Register, EL2
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