5.2 TLB organization

The Cortex-A72 processor implements a 2-level TLB structure.

The TLBs, at either the L1 or the L2 level, do not require to be flushed on a context or virtual machine switch. The MMU does not support the locking of TLB entries at either Level 1 or Level 2.
This section contains the following subsections:
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