Misses from the L1 instruction and data TLBs are handled by
a unified L2 TLB. This is a 1024-entry 4-way set-associative structure.
The L2 TLB supports the page sizes of 4K, 64K, 1MB and 16MB. It
also supports page sizes of 2MB and 1GB for the long descriptor
format translation in AArch32 state and in AArch64 state when using
the 4KB translation granule. In addition, the L2 TLB supports the
512MB page map size defined for the AArch64 translations that use
a 64KB translation granule.
Accesses to the L2 TLB take a variable number of cycles, based
on the competing requests from each of the L1 TLBs, TLB maintenance
operations in flight, and the different page size mappings in use.