6.1 About the L1 memory system

The L1 memory system consists of separate instruction and data caches.

The L1 instruction memory system has the following features:
  • 48KB 3-way set-associative instruction cache.
  • Fixed line length of 64 bytes.
  • Parity protection per 16 bits.
  • Instruction cache that behaves as Physically-indexed and physically-tagged (PIPT).
  • Least Recently Used (LRU) cache replacement policy.
  • MBIST support.
The L1 data memory system has the following features:
  • 32KB 2-way set-associative data cache.
  • Fixed line length of 64 bytes.
  • ECC protection per 32 bits.
  • Data cache that is PIPT.
  • Out-of-order, speculative, non-blocking load requests to Normal memory and non-speculative, non-blocking load requests to Device memory.
  • LRU cache replacement policy.
  • Hardware prefetcher that generates prefetches targeting both the L1 data cache and the L2 cache.
  • MBIST support.

Note

The Cortex-A72 processor does not support cache lockdown.
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