6.3 L1 instruction memory system
The instruction cache can source up to 128 bits per fetch depending on alignment.
Sequential cache read operations reduce the number of full cache reads. This has the
benefit of reducing power consumption. If a cache read is sequential to the previous cache
read, and the read is within the same cache line, only the data RAM way that was previously
read is accessed.
The L1 instruction cache appears to software as a physically tagged, physically indexed
array. Therefore, the instruction cache is only required to be flushed when writing new data
to an instruction address.
This section contains the following subsections: