An instruction remains in the pipeline between the fetch and
the execute stages. Because there can be several unresolved branches
in the pipeline, instruction fetches are speculative, meaning there
is no guarantee that they are executed. A branch or exceptional
instruction in the code stream can cause a pipeline flush, discarding
the currently fetched instructions.
Because of the aggressive prefetching behavior, you must not
place read-sensitive devices in the same page as code. Pages with
Device memory type attributes are treated as Non-cacheable Normal
Memory. You must mark pages that contain read-sensitive devices
with the TLB Execute Never (XN) attribute bit.
To avoid speculative fetches to read sensitive devices when
address translation is disabled, these devices and code that are
fetched must be separated in the physical memory map. See the ARM® Architecture
Reference Manual ARMv8 for more information. To avoid
speculative fetches to potential non-code regions, the static predictor
is disabled and branches are forced to resolve in order when address
translation is disabled.