All memory requests for pages that are marked as Inner Shareable in the page tables and are
Write-Back Cacheable, regardless of allocation policy, are coherent in all the caches that
comprise the inner domain. At a minimum, this includes the L1 data cache of the executing
the L2 cache, and all other L1 data caches in the
The inner domain might contain additional caches outside the
depending on how the system is configured.
It is unpredictable whether memory requests for pages that
are marked as Inner Non-shareable are coherent with the processor.
No code must assume that Non-shareable pages are incoherent among
The L1 data cache implements a MESI coherence protocol.