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ARM® Cortex®-A72 MPCore Processor Technical Reference ManualRevision r0p2
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6.4.3 Cache disabled behavior

When you clear the C bit in the CP15 System Control Register for a given processor, data caching is disabled and no new cache lines are allocated to the L1 data cache and L2 cache because of data requests from that processor. This is important when cleaning and invalidating the caches for power down.

Cache lines can be allocated from memory requests of other processors, unless their cache enable bits are also cleared. The effect on the L1 memory system is that all Write-Back Read-Write-Allocate pages are treated as Non-cacheable pages.
When you disable the cache, all Write-Back Cacheable requests do not look up the L1 data cache. L1 cache still services the snoops from the L2 cache.
Related information
4.5.5 System Control Register
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