You can enable the CPUACTLR[24], Non-cacheable streaming enhancement bit, only if your memory system meets the requirement that cache line fill requests from the processor are atomic. Specifically, if the processor requests a cache line fill on the AXI master read address channel, any given write request from a different master is ordered completely before or after the cache line fill read. This means that after the memory read for the cache line fill starts, writes from any other master to the same cache line are stalled until that memory read completes. Setting this bit enables higher performance for applications with streaming reads from memory types that do not allocate into the cache.

Because it is possible to build an AXI interconnect that does not comply with the specified requirement, the CPUACTLR[24] bit defaults to disabled.