The L1 data cache supports optional single bit correct and
double bit detect error correction logic in both the Tag and Data
arrays. The ECC granularity for the Tag array is the tag for a single
cache line and the ECC granularity for the Data array is a 32-bit
Because of the ECC granularity in the Data array, a write
to the array cannot update a portion of a 4-byte aligned memory
location because there is not enough information to calculate the
new ECC value. This is the case for any store instruction that does
not write one or more aligned 4-byte regions of memory. In this
case, the L1 data memory system reads the existing data in the cache,
merges in the modified bytes, and calculates the ECC from the merged
value. The L1 memory system attempts to merge multiple stores together
to meet the aligned 4-byte ECC granularity and to avoid the read-modify-write
Single bit ECC errors in the Tag or cache are corrected in the background. Because the line
is removed from the L1 cache as part of the correction process, no software intervention is
required. No exception or interrupt is generated. The CPU Memory Error Syndrome
is updated to indicate a nonfatal error.
Double bit ECC errors in the Tag or cache are detected and
an imprecise Data Abort is triggered. The line that contains the
error is evicted from the cache. When a double bit error is reported, you
must assume that data corruption has occurred and handle this appropriately.
For any detected ECC error in the L1 memory system, the CPU
Memory Error Syndrome Register is updated. For the first error reported,
the register is updated with information for the RAM, bank, way,
and index that contain the error. If that same location reports
multiple errors, the repeat error count is incremented. If any other
RAM locations report errors, the other error count is incremented.
Double-bit ECC errors set the fatal bit. When the register is written
with zeros, the register clears all counts and starts to monitor
for a new first error again.