6.5.2 Return stack predictions

The return stack stores the address and the ARM or Thumb state of the instruction after a function-call type branch instruction. This address is the same as the Link Register value stored in r14 in AArch32 state or X30 in AArch64 state. The following instructions cause a return stack push if predicted:
  • BL immediate.
  • BLX(1) immediate in AArch32 state.
  • BLX(2) register in AArch32 state.
  • BLR register in AArch64 state.
The following AArch32 instructions cause a return stack pop if predicted:
  • BX r14
  • MOV pc, r14.
  • LDMIA sp!, {..pc}.
  • LDR pc, [sp], #4.
The LDMIA and LDR instruction address modes are correspondent with popping the return address of a full descending stack. In AArch64 state, the RET instruction causes a return stack pop. There is no dependency on a specific return address target register, for example X30.
Because return-from-exception instructions can change the processor privilege mode and Security state, they are not predicted. This includes the ERET, RFE, and LDM(3) instruction, and the MOVS pc, r14 instruction.
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