8.2.5 nIRQ and nVFIQ inputs

The Cortex-A72 processor includes the virtual interrupt signals, nVIRQ and nVFIQ. There is one nVIRQ and one nVFIQ for each core.
  • If GICCDISABLE is tied HIGH, nVIRQ and nVFIQ can be:
    • Tied off to HIGH if they are not in use.
    • Driven by an external GIC in the SoC.
  • If GICCDISABLE is tied LOW and the GIC virtual CPU interface is enabled and in use, ARM recommends to tie nVIRQ and nVFIQ off to HIGH. This is because the internal GIC CPU interface generates the virtual interrupt signals to the cores.
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