8.3.6 Virtual CPU interface register summary

The virtual CPU interface forwards virtual interrupts to a connected Cortex-A72 processor, subject to the normal GIC handling and prioritization rules. The virtual interface control registers control virtual CPU interface operation, and in particular, the virtual CPU interface uses the contents of the List registers to determine when to signal virtual interrupts. When a core accesses the virtual CPU interface, the List registers are updated.

For more information on virtual CPU interface, see the ARM® Generic Interrupt Controller Architecture Specification, GICv3.
The following table shows the register map for the virtual CPU interface. The offsets in this table are relative to the virtual CPU interface block base address as shown in Table 8-1 Cortex-A72 processor GIC memory map.
All the registers in the following table are word-accessible. Registers not described in this table are Reserved.

Table 8-14 Virtual CPU interface register summary

Offset Name Type Reset Description
0x0000 GICV_CTLR RW 0x00000000 VM Control Register 
0x0004 GICV_PMR RW 0x00000000 VM Priority Mask Register a
0x0008 GICV_BPR RW 0x00000002 VM Binary Point Register a
0x000C GICV_IAR RO 0x000003FF VM Interrupt Acknowledge Register a
0x0010 GICV_EOIR WO - VM End Of Interrupt Register a
0x0014 GICV_RPR RO 0x000000FF VM Running Priority Register a
0x0018 GICV_HPPIR RO 0x000003FF VM Highest Priority Pending Interrupt Register a
0x001C GICV_ABPR RW 0x00000003 VM Aliased Binary Point Register a
0x0020 GICV_AIAR RO 0x000003FF VM Aliased Interrupt Acknowledge Register a
0x0024 GICV_AEOIR WO - VM Aliased End of Interrupt Register a
0x0028 GICV_AHPPIR RO 0x000003FF VM Aliased Highest Priority Pending Interrupt Register a
0x002C GICV_STATUSR RW - VM Error Reporting Status Register a
0x00D0 GICV_APR0 RW 0x00000000 VM Active Priority Register
0x00FC GICV_IIDR RO 0x0084043B VM CPU Interface Identification Register
0x1000 GICV_DIR WO - VM Deactivate Interrupt Register a
a See the ARM® Generic Interrupt Controller Architecture Specification GICv3 for more information. The System register counterparts of these registers are described in the ARM® Generic Interrupt Controller Architecture Specification GICv3. The virtual CPU interface System registers do not have a separate encoding from the physical CPU interface System registers but access is controlled from the appropriate system controls that the ARM® Generic Interrupt Controller Architecture Specification GICv3 describes.
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