9.3.1 AArch64 Generic Timer register summary

The following table shows the AArch64 Generic Timer registers. See the ARM® Architecture Reference Manual ARMv8 for information about these registers.

Table 9-2 AArch64 Generic Timer registers

Name Type Reset Width Description
CNTKCTL_EL1 RW -a 32-bit
Timer Control register (EL1)
CNTFRQ_EL0 RW b UNK 32-bit
Timer Counter Frequency register
CNTPCT_EL0 RO UNK 64-bit
Physical Timer Count register
CNTVCT_EL0 RO UNK 64-bit
Virtual Timer Count register
CNTP_TVAL_EL0 RW UNK 32-bit
Physical Timer TimerValue (EL0)
CNTP_CTL_EL0 RW
-c
32-bit
Physical Timer Control register (EL0)
CNTP_CVAL_EL0 RW UNK 64-bit Physical Timer CompareValue register (EL0)
CNTV_TVAL_EL0 RW UNK 32-bit
Virtual Timer TimerValue register
CNTV_CTL_EL0 RW -c 32-bit
Virtual Timer Control register
CNTV_CVAL_EL0 RW UNK 64-bit Virtual Timer CompareValue register
CNTVOFF_EL2 RW UNK 64-bit
Virtual Timer Offset register
CNTHCTL_EL2 RW
-d
32-bit
Timer Control register (EL2)
CNTHP_TVAL_EL2 RW UNK 32-bit
Physical Timer TimerValue register (EL2)
CNTHP_CTL_EL2 RW -c 32-bit Physical Timer Control register (EL2)
CNTHP_CVAL_EL2 RW UNK 64-bit
Physical Timer CompareValue register (EL2)
CNTPS_TVAL_EL1 RW UNK 32-bit
Physical Timer TimerValue register (EL2)
CNTPS_CTL_EL1 RW -c 32-bit
Physical Secure Timer Control register (EL1)
CNTPS_CVAL_EL1 RW UNK 64-bit
Physical Secure Timer CompareValue register (EL1)
a The reset value for bits[9:8, 2:0] is 0b00000.
b Only at EL3, otherwise this register is RO.
c The reset value for bit[0] is 0.
d The reset value for bit[2] is 0 and for bits[1:0] is 0b11.
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