The processor has the following reset signals that affect
the debug registers:
- This signal initializes the processor logic, including
the debug, Embedded Trace Macrocell (ETM),
breakpoint, watchpoint logic, and performance monitors logic. This
maps to a Cold reset that covers reset of the processor logic and
the integrated debug functionality.
- This signal resets some of the debug and performance
monitor logic. This maps to a Warm reset that covers reset of the
- This signal initializes the shared debug APB, Cross
Trigger Interface (CTI), and Cross Trigger
Matrix (CTM) logic. This maps to an external debug reset
that covers the resetting of the external debug interface and has no
impact on the processor functionality.